// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * SBC8641D Device Tree Source
 *
 * Copyright 2008 Wind River Systems Inc.
 *
 * Paul Gortmaker (see MAINTAINERS for contact information)
 *
 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
 */

/include/ "mpc8641si-pre.dtsi"

/ {
	model = "SBC8641D";
	compatible = "wind,sbc8641";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512M at 0x0
	};

	lbc: localbus@f8005000 {
		reg = <0xf8005000 0x1000>;

		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
			  1 0 0xf0000000 0x00010000	// 64KB EEPROM
			  2 0 0xf1000000 0x00100000	// EPLD (1MB)
			  3 0 0xe0000000 0x04000000	// 64MB LB SDRAM (CS3)
			  4 0 0xe4000000 0x04000000	// 64MB LB SDRAM (CS4)
			  6 0 0xf4000000 0x00100000	// LCD display (1MB)
			  7 0 0xe8000000 0x04000000>;	// 64MB OneNAND

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x01000000>;
			bank-width = <2>;
			device-width = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				label = "dtb";
				reg = <0x00000000 0x00100000>;
				read-only;
			};
			partition@300000 {
				label = "kernel";
				reg = <0x00100000 0x00400000>;
				read-only;
			};
			partition@400000 {
				label = "fs";
				reg = <0x00500000 0x00a00000>;
			};
			partition@700000 {
				label = "firmware";
				reg = <0x00f00000 0x00100000>;
				read-only;
			};
		};

		epld@2,0 {
			compatible = "wrs,epld-localbus";
			#address-cells = <2>;
			#size-cells = <1>;
			reg = <2 0 0x100000>;
			ranges = <0 0 5 0 1	// User switches
				  1 0 5 1 1	// Board ID/Rev
				  3 0 5 3 1>;	// LEDs
		};
	};

	soc: soc@f8000000 {
		ranges = <0x00000000 0xf8000000 0x00100000>;

		enet0: ethernet@24000 {
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		mdio@24520 {
			phy0: ethernet-phy@1f {
				reg = <0x1f>;
			};
			phy1: ethernet-phy@0 {
				reg = <0>;
			};
			phy2: ethernet-phy@1 {
				reg = <1>;
			};
			phy3: ethernet-phy@2 {
				reg = <2>;
			};
			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		enet1: ethernet@25000 {
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
		};

		mdio@25520 {
			tbi1: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		enet2: ethernet@26000 {
			tbi-handle = <&tbi2>;
			phy-handle = <&phy2>;
			phy-connection-type = "rgmii-id";
		};

		mdio@26520 {
			tbi2: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		enet3: ethernet@27000 {
			tbi-handle = <&tbi3>;
			phy-handle = <&phy3>;
			phy-connection-type = "rgmii-id";
		};

		mdio@27520 {
			tbi3: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};
	};

	pci0: pcie@f8008000 {
		reg = <0xf8008000 0x1000>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		interrupt-map-mask = <0xff00 0 0 7>;

		pcie@0 {
			ranges = <0x02000000 0x0 0x80000000
				  0x02000000 0x0 0x80000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
		};

	};

	pci1: pcie@f8009000 {
		reg = <0xf8009000 0x1000>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;

		pcie@0 {
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
		};
	};
};

/include/ "mpc8641si-post.dtsi"
